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DSP |
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| ADSP-21065
BASED TRAINER KITS |
| Micro-
21065 |
Features
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ADSP-21065 DSP Processor running at 15ns instruction
cyclefime
Super Harvard Architecture Computer(SHARC) with four
independent Buses for dual Data instruction, and I/O
Fetch on single cycle.
32-bit Fixed -point Arithmetic
32-bit and 40-bit Floating point Arithmetic.
Code compatible with ADSP-2106X family.
12-programmable I/O pins and two timers with event
capture options.
10-DMA channels.
208 Lead MQFP or 196-Ball Mini-BGA package.
3.3 Volt operation.
66 MIPS, 198 MFLOPS.
64m
words external/address range |
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BlackFin 
