8251 & 8253 INTERFACE BOARD: [VBMB-004]					8259 SIMULATOR BOARD: [VBMB-006]
Incorporates INTEL 8253 timer & USART 8251. Provision to give External/Internal/ Manual input clock to 8253. Output of channel 2 to CPUs interrupt. Baud rate generation for 8251 using 8253. Standard RS232C serial port in a 9 Pin 'D' Male Connector. All timer inputs/outputs terminated . Loop back provision to check the serial port. Provision for test points & fault analysis points .					Specifically designed to learn the internal operation of INTEL 8259.  3 DIP Switches decide the starting address of ISR. Options to choose either with 8085 CPU or with 8086/88 CPU. Provision to study the complete internal timing of INTEL 8259. Provision for test points & fault analysis points.

8259 INTERFACE BOARD: [VBMB-007]					8255 INTERFACE BOARD: [VBMB-008]
Incorporates INTEL 8259, Programmable Interrupt Controller Chip. 8 switches provided for giving interrupts. 8 IRQ lines terminated at a 10 Pin Header. Compatible with 8085, 8088/86 CPU Based Microprocessor Kits. Provision for test points & fault analysis points.					Incorporates INTEL 8255, Programmable Peripheral Interface Chip. All essential extra hardware provided to operate 8255 in Mode 0 or Mode 1 or Mode 2. 8 Nos. of SPDT Switches provided at Port A for giving 8 TTL inputs . 8 Nos. of LED's provided at Port B for outputs Provision to interrupt the CPU in Mode 1 and Mode 2 All the ports lines are terminated in a standard 26 Pin Header FRC connector. Provision for test points & fault analysis points  5 Nos. of LED's provided at port "C"  3 Instrument type high quality switch with debouncing logic provided

DMA INTERFACE BOARD:[VBMB-011]					RAM / ROM INTERFACE TRAINER: [VBMB-024A]
Designed to demonstrate the INTEL 8237 Direct Memory Access Controller.  One 8-bit input port with DIP Switch. One 8-bit output port with LEDs. 8K 8-bit static RAM to explain the memory to memory transfer. Facility to demonstrate HOLD and HLDA timing. Provision to give hardware DMA requests. Provision for test points & fault analysis points					A ZIF socket provided to insert RAM/EPROM under study.  Provision to study the Read/Write waveform timing diagram of popular RAM/EPROMS as 6264, 62256, 2764A and 27256. Study the importance of CE! and OE! signals.

FLASH MEMORY PROGRAMMER [VBMB-031]					EPROM PROGRAMMER INTERFACE BOARD: [VBMB-024]
Interface with 8086 Trainer Kit 512K of flash RAM is provided (AM290F40B) Erase, Read & Write operations can be done Fully buffered address, data & Control signals terminated at a 50 pin header (VXT Bus) for interfacing with trainer Provision for higher order address and data lines termination 50 Core Cable					EPROM Programmer Interface Programs devices from 2716 to 27512.  Programming voltage selection through software. Functions: Read, Program, Verify and Blank check. Device and function selection through software.  28 pin ZIF socket provided on board

PRINTER INTERFACE BOARD:[VBMB-005]					PRINTER SIMULATION BOARD: [VBMB-005A]
Centronics Compatible Printer Interface. Loop-back provision to check the working of the port. Facility for Interrupt based I/O transfer. Printer Control and status signals monitored using LED's. Provision for test points & fault analysis points.					Specifically designed to demonstrate the centronics printer interface. Can be set in manual or auto mode. Facility to send ASCII DATA to the printer with eight SPDT switches. Facility to print a particular data continuously. LED's are provided to show the status of the printer. Provision to give strobe using debounce circuitry of NC/NO switch.

CRO INTERFACE BOARD: [VBMB-010]					FDC INTERFACE BOARD: [VBMB-012]
Two 8-bit ports to select character and its position. Two channel 8-bit DAC for X and Y inputs of CRO. Facility to control the Z-modulation input of the CRO. 8KB Character generator for alpha-numeric or graphic characters. Provision for test points & fault analysis points .					Incorporates the single chip Floppy Disk Controller 8398. Supports up to 2 drives (maximum) . 1.44MB format selectable by software which depends on Microprocessor Kit's speed and capacity. IBM PC compatible I/O decoding. Internal write pre compensation and data separation. Data transfer through Polling / Interrupt. LEDs are provided to monitor the status of disk drive.

STEPPER MOTOR CONTROLLER WITH MOTOR [VBMB-013A]					TWO STEPPER MOTOR CONTROLLER [VBMB-013A]
Driver provided for controlling one stepper motor. Can control Stepper motors ranging from 2Kg to 20Kg.  Provision for connecting external power supply of 6V, 12V or 24V, selectable by jumpers. One 2Kg/12V Stepper Motor.					Drivers provided for controlling two stepper motors. Two TTL I/O inputs for sensing limit switch. Can control Stepper motors ranging from 2Kg to 20Kg. Provision for connecting external power supply of 6V, 12V or 24V, selectable by jumpers.

REAL TIME CLOCK / CALENDER BOARD: [VBMB-015]					DC MOTOR SPEED MEASUREMENT & CONTROL MODULE : [VBMB-017]
Based on MSM 6242 Read Time Clock/ Calender Chip. Data/Time programmable by Microprocessor. Four Digit Seven Segment LED Display for Time/Date display. 3.6V rechargeable Ni-Cd battery backup. Interrupt facility for interrupting the CPU. Test and fault analysis points for debugging .					8 Bit DAC to control the speed and direction of DC motor. 6V DC motor with slotted disk . Optical pickup with wave shaping circuitry for speed sensing. Speed measurement through 8253 . Counter channel 0 is used for measuring the speed of the DC motor . Channel 1 and Channel 2 of 8253 is fully made available for the user Designed for teaching DC motor control fundamentals.

ELEVATOR SIMULATOR INTERFACE: [VBMB-022]					Interfacing push to ON Switches and Relays [VBMB-037]
8 floors and 2 lifts are assumed. Each Lift is represented by a column of 8 LED's. Preset thumb wheel switch is provided for the user to select the floor number. One Momentary switch provided for the user to confirm their request input. Two Momentary switches provided for UP and DOWN movement request Buzzer and an LED are provided for Audible and visual Error status indication. Provision for interrupt driven request service.					SPDT Switches and Relays provided to study the interface to push to ON switches and relays Two switches provided for level triggering for generating the interrupts to 8051/89C51 Four nos. of Relays provided. Two switches provided for edge-triggering (Jumber selectable & Software selectable) Four nos. of LEDs provided for output indication 32KB EPROM Provided to interface the above setup with out 8051/89C51 Microcontroller trainer kit Software provided for generating timer interrupts 40 pin Cable will be provided. Detailed manual for full exercise of interrupt study of 8051/89C51.